Sugarbox 0.15 is out.

A new version is available : Sugarbox v0.15

It’s mainly focused on the CRTC1 and monitor emulation (with some correction on Z80 core)

Here’s what’s new :

- CRTC detection tests are correctly passed (For CRTC 1 at least)
- Z80 : Lots of improvement in Interrupt and general timings
- Z80 : OUT write it’s value with delay to the port (this make some demo works..)
- Z80 : When an interrupt is pending, EI / HALT works correctly (this make « L’arche du capitaine blood » original dump to work correctly)
- CRTC : Fix the adress computation : Only correct bits are compared. This correct the « The demo » demo.
- CRTC1 : Fix adjustement computation, when R5 > R9 (adjustement counter was only increased when VCC=R4)
- Gate Array : Corrected a bug in the MMR, that prevented Phortem demo to run
- Gate Array : IO handled at 4mhz to have precise timings for color changed
- Ink changed should be pixel correct
- PPI8255 : CPC+ Feature of non-reset of Port ABC when writing control register implemented. This allow CRTC detection to be complete
- PPI8255 : Corrected a bug in PPI Control register, when bit7=0 (Shadow of the beast hanging bug in « press fire » screen is corrected)
- PPI8255 : Port B only readable.
- FDC : Read Track correction, LATIS (Hercule2 – Translock) now ok
- FDC : Detection of end disk improved, even when GAP3 is wrong
- FDC : Disk with only MV – CPC now loads correctly
- Monitor : Correction of a bug that prevented a detection of HBL in some case of the PLL ->Arkanoid I no longer crash the emulator
- Monitor : Rewrite the honrizontal synchronization mechanism.
- Monitor : Correction of HSync. CRTC R0=64 can be used now without hsync problems (The demo work better)
- Monitor : Improved handling of Hsync position via R2
- Monitor : Correct the garbage that occasionnaly appear on reset
- Monitor : Add handling of multiple HSync with correct synchronisation
- Reset is now fully implemented
- Settings : CRTC type is changed correctly
- Settings : Change does no longer reboot the CPC


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